A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks

نویسندگان

  • Philippe Hoogvorst
  • Sylvain Guilley
  • Sumanta Chaudhuri
  • Jean-Luc Danger
  • Taha Beyrouthy
  • Laurent Fesquet
چکیده

Side-channel attacks are efficient attacks against cryptographic devices. They use only quantities observable from outside, such as the duration and the power consumption. Attacks against synchronous devices using electric observations are facilitated by the fact that all transitions occur simultaneously with some global clock signal. Asynchronous control remove this synchronization and therefore makes it more difficult for the attacker to insulate interesting intervals. In addition the coding of data in an asynchronous circuit is inherently more difficult to attack. This article describes the Programmable Logic Block of an asynchronous FPGA resistant against side-channel attacks. Additionally it can implement different styles of asynchronous control and of data representation.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback

This article presents an asynchronous FPGA architecture for implementing cryptographic algorithms secured against physical cryptanalysis. We discuss the suitability of asynchronous reconfigurable architectures for such applications before proceeding to model the side channel and defining our objectives. The logic block architecture is presented in detail. We discuss several solutions for the in...

متن کامل

A Reconfigurable Cell for a Multi-Style Asynchronous FPGA

At the opposite of synchronous designs, in which the validity of signal is guranteed by the occurence of the clock signal, in asynchronous designs, the signals carry at the same time the validity and the value informations. Various protocols have been designed to implement this representation, all of them having in common that signals consists of more than a single electric voltage. A logical s...

متن کامل

Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture

This paper presents a novel architecture to increase the hardware utilization in multi-context field programmable gate arrays (MCFPGAs). Conventional MC-FPGAs use dedicated tracks to transfer context-ID bits. As a result, hardware utilization ratio decreases, since it is very difficult to map different contexts, area efficiently. It also increases the context switching power, area and static po...

متن کامل

FPGA Architecture for Multi-Style Asynchronous Logic

This paper presents a novel FPGA architecture for implementing various styles of asynchronous logic. The main objective is to break the dependency between the FPGA architecture dedicated to asynchronous logic and the logic style. The innovative aspects of the architecture are described. Moreover the structure is well suited to be rebuilt and adapted to fit with further asynchronous logic evolut...

متن کامل

Reconfigurable Processing Framework for Space-Time Block Codes

Space-time block coding has emerged in recent years as a promising research topic to enable future high-speed wireless communications networks and services. A considerable number of authors have developed algorithms and techniques that have been explored in simulations. However, fully implemented systems are rare. This paper considers the use of reconfigurable logic for implementing space-time ...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:
  • CoRR

دوره abs/0809.3942  شماره 

صفحات  -

تاریخ انتشار 2008